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DS1123L
3.3V, 8-Bit, Programmable Timing Element
_____________________________________________________________________
7
AC ELECTRICAL CHARACTERISTICS (DS1123L-200)
(VCC = +3.0V to 3.6V, TA = 0°C to +70°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Reference Delay
tREF
(Notes 3, 4)
18
22
ns
Delay Step Size
tSTEP
TA = +25°C
1.0
2
3.0
ns
Step-Zero Delay with Respect
to IN
tD0
(Notes 4, 5)
16.5
22
ns
Step-Zero Delay with Respect
to REF
tD0REF
(Notes 6, 7)
-2.5
-1.5
0
ns
Maximum Delay with Respect
to IN
tDMAX
(Notes 4, 8)
527
ns
Delay with Respect to REF
tDREF
Position FF (Notes 7, 9)
510
ns
Delay with Respect to REF
Tolerance
VCC = 3.3V, TA = +25°C
(Notes 7, 9)
-0.75
+0.75
%
Voltage Delay Variation
(Notes 7, 9)
-0.5
+0.5
%
Temperature Delay Variation
VCC = 3.3V
-2.5
+2.5
%
Integral Nonlinearity (Deviation
from Straight Line)
terr
(Note 10)
-5
0
+5
ns
OUT Delta Delay
tINV0
(Note 11)
0
1
2.5
ns
IN High to PWM High
tPWM0
(Notes 4, 12)
16.5
22
ns
Minimum PWM Output Pulse
Width
tPWM
(Note 13)
5
ns
Minimum Input Pulse Width
tWI
(Note 14)
40
ns
Minimum Input Period
(Note 15)
80
ns
Input Rise and Fall Times
tr, tf
(Note 16)
0
1
μs
Note 10:
See the
Integral Nonlinearity section and Figure 9.
Note 11:
Change in delay value when the inverted output is selected instead of the normal, noninverting output.
Note 12:
In PWM mode, the delay between the rising edge of the input and the rising edge of the output.
Note 13:
The minimum value for which the monostable-vibrator pulse width should be programmed. Narrower pulse widths can be
programmed, but output levels may be impaired and ultimately no output pulse is produced.
Note 14:
This is the minimum allowable interval between transitions on the input to assure accurate device operation. This parame-
ter may be violated, but timing accuracy may be impaired and ultimately very narrow pulse widths result in no output from
the device.
Note 15:
This parameter applies to normal delay mode only. When a 50% duty cycle input clock is used this defines the highest
usable clock frequency. When asymmetrical clock inputs are used, the maximum usable clock frequency must be
reduced to conform to the minimum input pulse-width requirement. In PWM mode, the minimum input period is equal to
the step-zero delay and the programmed delay (tDO +tD).
Note 16:
Faster rise and fall times give the greatest accuracy in measured delay. Slow edges (outside the specification maximum)
can result in erratic operations.
Δt
t
DREF
Δt
t
DV
DREF
Δt
t
DT
DREF
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